CMOS image sensor and method of fabricating the same

ABSTRACT

A CMOS image sensor and a method of fabricating the same are provided. The image sensor includes a blocking layer protecting a photodiode at a diode region. The blocking layer is formed to cover a top of the diode region and extended to an active region so as to cover a transfer gate and a floating diffusion layer. Therefore, the floating diffusion layer may not be attacked by an etching during a formation of sidewall spacers of various gates or by ion implantation during a formation of a junction region of a DDD or LDD structure, thus reducing a leakage current and a dark current at the floating diffusion layer.

FIELD OF THE INVENTION

[0001] The present invention relates generally to a CMOS image sensorand methods of fabricating the same and, more specifically, to a CMOSimage sensor having a reduced a dark current and fabrication methodsthereof.

BACKGROUND OF THE INVENTION

[0002] A CMOS image sensor transforms optical images to electricalsignals using CMOS technologies. The CMOS image sensor employs aswitching method that sequentially generates signals using MOStransistors. The CMOS image sensor has several advantages such as asimple operation process, low fabrication costs and low powerconsumption. On the contrary, a charge coupled device (CCD) image sensoris difficult to fabricate compared to the CMOS image sensor andimpossible to access randomly. Since the late 1990s, fabrication methodsof CMOS technologies and signal processing algorithms thereof have beenimproved. Therefore, many disadvantages of the CMOS have been overcome.Moreover, the CCD technology has been partially employed in the CMOSimage sensor, so that product qualities of the CMOS image sensor havebeen further improved.

[0003]FIG. 1 is a schematic circuit diagram of a typical CMOS imagesensor 100.

[0004] Referring to FIG. 1, the typical CMOS image sensor 100 includes aphotodiode Pd, a transfer transistor Tx, a reset transistor Rx, aselection transistor Sx and an access transistor Ax. The transfertransistor Tx and the reset transistor Rx are connected in serial to thephotodiode Pd. An applied voltage Vdd is supplied to a drain of thereset transistor Rx. A drain of the transfer transistor Tx (i.e., asource of the reset transistor Rx) corresponds to a floating diffusionlayer (F/D). The floating diffusion layer (F/D) is connected to a gateof the selection transistor Sx. The selection transistor Sx and theaccess transistor Ax are connected in serial and an applied voltage Vddis supplied to a drain of the selection transistor Sx.

[0005] An operation method of the CMOS image sensor 100 will beexplained as follows.

[0006] First, the reset transistor Rx is turned on, so that a voltage ofthe floating diffusion layer (F/D) becomes the applied voltage Vdd. Iflight is incident to the photodiode Pd, electron-hole pairs (EHPs) aregenerated and signal electrons are accumulated in a source of thetransfer transistor Tx. When the transfer transistor Tx is turned on,the accumulated signal electrons are transferred to the floatingdiffusion layer (F/D) to change a voltage of the floating diffusionlayer (F/D). At same time, a gate voltage of the selection transistor Sxchanges to the voltage of the floating diffusion layer. When a selectionsignal Row turns on the access transistor Ax, the applied voltage Vdd istransferred to an output terminal Out. Then, the reset transistor Rx isturned on again and the voltage of the floating diffusion layer (F/D) ismade equal to the applied voltage Vdd. Through repeating these steps,image signals are generated.

[0007]FIG. 2 is a top plan view of a typical CMOS image sensor.

[0008] Referring to FIG. 2, the CMOS image sensor includes a deviceisolation pattern 56 that is formed in a substrate to define a dioderegion 40 and an active region 42. Conventionally, the diode region 40is formed to be wide so as to increase a photo efficiency. The activeregion 42 is extended from a side of the diode region 40. Transfer gates64 and 24, reset gates 66 and 26 and selection gates 68 and 28 areserially formed and separated by a predetermined distance. Although notillustrated in the drawings, an access gate is formed separate from theselection gates 68 and 28 by a predetermined distance. The transfer gateTx is formed in the active region 42 adjacent to the diode region 40.Floating diffusion layers 70 and 38 are formed in the active region 42between the transfer gates 64 and 24 and the reset gates 66 and 26.Although not illustrated in the drawings, the floating diffusion layers70 and 38 and the selection gate 68 and 28 are electrically connectedthrough interconnections.

[0009]FIGS. 3 and 4 are cross-sectional views taken along line A-A ofFIG. 2 for illustrating steps of fabricating a conventional CMOS imagesensor.

[0010] Referring to FIG. 3, a deep P well 12 is formed in asemiconductor substrate. The deep P well 12 may be formed in a substratebetween a P type epitaxial layer 10 a and a silicon substrate 10. Byimplanting impurities into the P type epitaxial layer 10 a, a P well 14is formed in the P type epitaxial layer 10 a. The P well 14 is formedadjoining a diode region 40 of FIG. 2 that will be defined in asubsequent process. A device isolation pattern 16 of FIG. 2 is formed todefine an active region 42 of FIG. 2 and the diode region 40 of FIG. 2.An N type channel diffusion layer 22 is formed in an active region 42 ofFIG. 2 adjacent to the diode region 40 of FIG. 2. A transfer gate 24, areset gate 26 and a selection gate 28 are serially formed on the activeregion 42 of FIG. 2 separated from each other. The transfer gate 24 isformed on the N type channel diffusion layer 22.Impurities are implantedinto the diode region 40 of FIG. 2 to form an N type photodiode 18. A Ptype photodiode 20 is formed on the N type photodiode 18. The N type andP type photodiodes 18 and 20 may be formed prior to forming the gates.

[0011] Next, the impurities are implanted into the active region 42 ofFIG. 2 to form lightly doped diffusion layers 30 and 32 aligned tosidewalls of the transfer, reset and selection gates 24, 26 and 28.

[0012] Referring to FIG. 4, an insulation layer is formed on an entiresurface of the substrate with the lightly doped diffusion layers 30 and32. A photoresist pattern is formed to cover the diode region 40 of FIG.2 and expose the active region 42 of FIG. 2. Next, using the photoresistas an etch mask, the insulation layer is anisotropically etched to forma blocking layer 34 a covering the diode region 40 of FIG. 2 andsidewall spacers 34 b on sidewalls of the transfer gate 24, the resetgate 26 and the selection gate 28. Then, the photoresist is removed. Inthe conventional CMOS image sensor, the blocking layer 34 a covers thediode region 40 of FIG. 2 and is extended in a lateral direction toconformally cover a portion of a top surface and a sidewall of thetransfer gate 24. Using the blocking layer 34 a, the gates 24, 26 and 28and the sidewall spacers 34 b as an etching mask, impurities areimplanted into the substrate to form heavily doped diffusion layers 36,which are aligned to outer edges of the sidewall spacers 34 b, in thelightly doped diffusion layers 30 and 32. As a result, diffusion layerswith a DDD (double doped drain) structure are formed in the activeregion 42 of FIG. 2. Alternatively, diffusion layers with a LDD (lightlydoped drain) structure may be formed in the active region 42 of FIG. 2.The lightly and heavily doped diffusion layers 30 and 36 between thetransfer gate 24 and the reset gate 26 compose a floating diffusionlayer 38 of an image sensor.

[0013] According to the prior art, after covering the diode region 40 ofFIG. 2, the insulation layer is etched anisotropically, so that asurface of the P type photodiode 20 may be protected from beingattacked. Therefore, a dark current can be drastically reduced at asurface of the P type photodiode 20. However, during a formation of thesidewall spacers 34 b, a surface of the active region, where thefloating diffusion layer 38 is formed, may be damaged from etching andcrystalline defects of the active region can occur due to high energy ofthe ions during the formation of the heavily doped diffusion layers 36.Therefore, a leakage current pass is created at the floating diffusionlayer 38, so that a voltage of the floating diffusion layer 38 may notbe increased. As a result, output signals may be leveled down or not begenerated. In addition, if the diffusion is formed to have an LDDstructure, the floating diffusion layer 38 will have a large probabilityof suffering from a leakage current due to a high voltage between theheavily doped diffusion layers 36 and the P well 14.

SUMMARY OF THE INVENTION

[0014] It is an aspect of the present invention to provide a CMOS imagesensor having a reduced a leakage current of a floating diffusion layerand a method of fabricating the same.

[0015] It is another aspect of the present invention to provide a CMOSimage sensor having a decreased a dark current of a floating diffusionlayer and a method of fabricating the same.

[0016] According to one aspect of the present invention, a CMOS imagesensor of an embodiment of the present invention includes a deviceisolation pattern that is formed in a substrate and defining a dioderegion and an active region. A photodiode is formed in the diode regionand a transfer gate is formed in the active region adjacent to thephotodiode. A reset gate and a selection gate are serially formed on theactive region separated from the transfer gate by a predetermineddistance. The reset gate and the selection gate are separated from eachother. A floating diffusion layer is formed in the active region betweenthe transfer gate and the reset gate. A blocking layer protecting thephotodiode is formed on the diode region. The blocking layer is extendedto the active region to cover tops of the transfer gate and the floatingdiffusion layer. Therefore, the blocking layer prevents the floatingdiffusion layer from being attacked so as to significantly reduce aleakage current and a dark current occurring at the floating diffusionlayer.

[0017] According to the another aspect of the present invention, amethod of fabricating a CMOS image sensor comprises as follows. A deviceisolation pattern is formed in a substrate so as to define a dioderegion and an active region and a photodiode is formed in the dioderegion. A transfer gate, a reset gate and a selection gate are seriallyformed and laterally separated from each other by a predetermineddistance. In this case, the transfer gate is formed on the active regionadjacent to the diode region. A floating diffusion layer is formed inthe active region between the transfer gate and the reset gate. At thesame time, lightly doped diffusion layers are formed in active regionsbetween the reset gate and the selection gate and an active regionadjacent to the selection gate. Sidewall spacers are formed on asidewall of the reset gate facing the selection gate and sidewalls ofthe selection gate. In this case, a blocking layer is formed to cover atop of the diode region and extended to the active region to cover thetransfer gate and the floating diffusion layer. Finally, impurities areimplanted into the active regions to form heavily doped diffusionlayers, which are aligned to outer surfaces of the sidewall spacers, inthe lightly doped diffusion layers. The floating diffusion layer isprotected by the blocking layer and may not be attacked by the etchingduring a formation of the sidewall spacers or by the ion implantationduring a formation of the heavily doped diffusion layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 is a schematic circuit diagram of a typical CMOS imagesensor;

[0019]FIG. 2 is a top plan view of a typical CMOS image sensor;

[0020]FIGS. 3 and 4 are cross-sectional views illustrating steps offabricating a conventional CMOS image sensor;

[0021]FIG. 5 is a cross-sectional view of a CMOS image sensor inaccordance with an embodiment of the present invention; and

[0022] FIGS. 6-8 are cross-sectional views illustrating steps offabricating a CMOS image sensor in accordance with an embodiment of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0023] The present invention will now be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the invention are shown. This invention may,however, be embodied in different forms and should not be constructed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart. In the drawings, the thickness of layers and regions areexaggerated for clarity. It will also be understood that when a layer isreferred to as being “on” another layer or substrate, it can be directlyon the other layer or substrate or intervening layers may also bepresent. Like numbers refer to like elements throughout thespecification.

[0024]FIG. 5 is a cross-sectional view of a CMOS image sensor inaccordance with a preferred embodiment of the present invention.

[0025] Referring to FIG. 5, a CMOS image sensor according to anembodiment of the present invention includes a device isolation pattern56 defining a diode region 40 of FIG. 2, an active region 42 of FIG. 2and a deep P type well 52 that are formed in a substrate, and P typewell 54 formed in a substrate adjacent to the diode region 40 of FIG. 2.

[0026] A transfer gate 64, a reset gate 66 and a selection gate 68 areserially disposed on the active region 42 of FIG. 2. An N type channelregion 62 is formed in a substrate beneath the transfer gate 64 and afloating diffusion layer 70 is formed in an active region between thetransfer gate 64 and the reset gate 66. The CMOS image sensor of thepresent invention includes a blocking layer 74 a conformally coveringtops of the diode region 40 of FIG. 2, the transfer gate 64 and thefloating diffusion layer 70. The blocking layer 74 a may be extended ina lateral direction to cover a sidewall and a portion of a top surfaceof the reset gate 66. Sidewall spacers 74 b are formed on the othersidewall of the reset gate 66 and both sidewalls of the selection gate68. Lightly doped diffusion layers 72 are formed in active regionsbetween a sidewall of the reset gate 66 and a sidewall of the selectiongate 68, which face each other, and in an active region adjacent to theopposite sidewall of the selection gate 68. The lightly doped diffusionlayers 72 are aligned to the sidewalls of the reset gate 66 and theselection gate 68. Heavily doped diffusion layers 76 aligned to outersurfaces of the sidewall spacers 74 b are formed in each of the lightlydoped diffusion layers 72, respectively. The lightly and heavily dopeddiffusion layers 72 and 76 correspond to a junction region of atransistor. The junction region may be formed to have a double dopeddrain (DDD) or a lightly doped drain (LDD) structure. As illustrated inFIG. 5, a floating diffusion layer 70 of the CMOS image sensor may havea single-layered structure and a top thereof is covered with a blockinglayer 74 a. Therefore, etching and implantation damage may be preventedduring the fabrication processes, so that a leakage current and a darkcurrent occurring at the floating diffusion layer can be drasticallyreduced.

[0027] In addition, protection layers 78 may be formed on tops of theblocking layer 74 a and the sidewall spacers 74 b, respectively, andsalicide layers 80 may be formed in the heavily doped diffusion layers76 aligned to sidewalls of the protection layer 78.

[0028] FIGS. 6-8 are cross-sectional views illustrating steps offabricating a CMOS image sensor in accordance with a preferredembodiment of the present invention.

[0029] Referring to FIG. 6, a deep P well 52 is formed in a substrate byimplanting impurities into the substrate. The substrate may be formed bystacking a P type epitaxial layer 50 a on a silicon substrate 50. Thedeep P well 52 may be formed at a boundary region between the siliconsubstrate 50 and the P type epitaxial layer 50 a by implantingimpurities into the P type epitaxial layer 50 a. The deep P well 52 isdoped with a concentration higher than that of the P type epitaxiallayer 50 a.

[0030] A device isolation pattern 56 is formed in the substrate todefine a diode region 40 of FIG. 2 and an active region 42 of FIG. 2. AP well 54 is formed in the P type epitaxial layer 50 a adjacent to thediode region 40 of FIG. 2. An N type channel diffusion layer 62 isformed in the active region 42 of FIG. 2 adjacent to the diode region 40of FIG. 2. The P well 54 is doped with a concentration higher than thatof the P type epitaxial layer 50 a. An N type photodiode 58 is formed inthe diode region 40 of FIG. 2. A P type photodiode 60 is formed on the Ntype photodiode 58. The N type photodiode 58 is preferably connected tothe N type channel diffusion layer 62 and the P type photodiode 60 ispreferably connected to the P well 54.

[0031] Referring to FIG. 7, a transfer gate 64, a reset gate 66 and aselection gate 68 are serially formed on the active region 42 of FIG. 2separated from each other by a predetermined distance. Different fromthe previously mentioned steps, the P well 54 may be formed prior toforming the device isolation pattern 56, and the N type channeldiffusion layer 62, the N type photodiode 58, the P type photodiode 60and the gates 64, 66 and 68 may be formed in different orders. That is,the N type and P type photodiodes 58 and 60 may be formed after formingthe gates. Impurities are implanted into active regions among thetransfer gate 64, the reset gate 66 and the selection gate 68, therebyforming an N type floating gate 70 in an active region between thetransfer gate 64 and the reset gate 66, and a N type lightly dopeddiffusion layer 72 in an active region at both sides of the selectiongate 68. An insulation layer 74 is formed on an entire surface with thefloating diffusion layer 70 and the lightly doped diffusion layers 72. Aphotoresist pattern 75 is formed on the insulation layer 74 to covertops of the P type photodiode 60, the transfer gate 64 and the floatingdiffusion layer 70. The photoresist pattern 75 may be extended in alateral direction, thereby covering a portion of a top of the reset gate66.

[0032] Referring to FIG. 8, using the photoresist pattern 75 as an etchmask, the insulation layer 74 is etched to form a blocking layer 74 acovering tops of the P type photodiode 60, the transfer gate 64 and thefloating diffusion layer 70. Sidewall spacers 74 b are formed on asidewall of the reset gate 66 and a sidewall of the selection gate 68,which face each other, and the other sidewall of the selection gate 68,respectively. Next, impurities are implanted into the active region toform N type heavily doped diffusion layers 76. The N type heavily dopeddiffusion layers 76 are aligned to outer edges of the sidewall spacers74 b. The heavily and lightly doped diffusion layers 76 and 72 may beformed to construct a DDD structure as illustrated in FIG. 8 or to havean LDD structure. Contrary to the prior art, the floating diffusionlayer 70 of an embodiment of the present invention may not be attackedby an etching during a formation of the sidewall spacers 74 b or by anion implantation during a formation of the heavily doped diffusionlayers 76. Thus, crystalline defects causing a leakage current and adark current can be reduced.

[0033] Next, using a conventional method, protection layers 78 of FIG. 5are formed to cover tops of the blocking layer 74 a and the sidewallspacers 74 b, respectively and then salicide layers 80 of FIG. 5 alignedto the protection layers 78 may be formed on the active region.

[0034] According to embodiments of the present invention, a blockinglayer covering a top of a diode region is extended in a lateraldirection to cover a floating diffusion layer, thereby reducing aleakage current and a dark current occurring at the floating diffusionlayer. Therefore, CMOS image sensors outputting high quality signals canbe achieved.

What is claimed is:
 1. A CMOS image sensor comprising: a deviceisolation pattern formed in a substrate to define a diode region and anactive region; a photodiode formed in the diode region; a transfer gateformed adjoining the photodiode on the active region; a reset gate and aselection gate serially formed apart from each other on the activeregion separated from the transfer gate by a predetermined distance; afloating diffusion layer formed in the active region between thetransfer gate and the reset gate; and a blocking layer formed on thediode region so as to protect the photodiode, wherein the blocking layeris extended to the active region to cover tops of the transfer gate andthe floating diffusion layer.
 2. The CMOS image sensor of claim 1,wherein the blocking layer further covers a predetermined region of atop of the reset gate.
 3. The CMOS image sensor of claim 1, furthercomprising: lightly doped diffusion layers formed in an active regionbetween the reset gate and the selection gate and in an active regionadjacent to the selection gate; sidewall spacers formed on a sidewall ofthe reset gate facing the selection gate and on sidewalls of theselection gate; and heavily doped diffusion layers, which are aligned tothe sidewall spacers, formed in the lightly doped diffusion layers. 4.The CMOS image sensor of claim 3, further comprising: a protection layerformed on the blocking layer and sidewall spacers, respectively; and asalicide layer aligned to the protection layer formed on the heavilydoped diffusion layers.
 5. The CMOS image sensor of claim 1, wherein thephotodiode further comprises: an N type photodiode formed in the dioderegion; and a P type photodiode formed at a surface of the diode regionon the N type photodiode.
 6. The CMOS image sensor of claim 5, furthercomprising an N type channel diffusion layer formed in an active regionbeneath the transfer gate, wherein the channel diffusion layer and the Ntype photodiode are in contact with each other.
 7. The CMOS image sensorof claim 5, further comprising a P type well formed in the substrateadjacent to the diode region, wherein the P type photodiode is connectedto the P type well.
 8. The CMOS image sensor of claim 5, furthercomprising a deep P well formed in the substrate beneath the N typephotodiode.
 9. A method of fabricating a CMOS image sensor comprising:forming a device isolation pattern to define a diode region and anactive region in a substrate; forming a photodiode in the diode region;serially forming a transfer gate, a reset gate and a selection gateseparated from each other by a predetermined distance, wherein thetransfer gate is formed on the active region adjacent to the dioderegion; forming a floating diffusion layer in the active region betweenthe transfer gate and the reset gate and lightly doped diffusion layersin active regions at both sides of the selection gate; forming sidewallspacers on a sidewall of the reset gate facing the selection gate andsidewalls of the selection gate; simultaneously forming a blocking layercovering a top of the diode region and extended to the active region tocover the transfer gate and the floating diffusion layer; and implantingimpurities into the active regions to form heavily doped diffusionlayers that are aligned to outer surfaces of the sidewall spacers in thelightly doped diffusion layers.
 10. The method of claim 9, wherein thephotodiode is formed after forming the transfer gate, the reset gate andthe selection gate.
 11. The method of claim 9, wherein the forming thephotodiode comprises: implanting impurities into the diode region so asto form an N type photodiode in a predetermined depth of the dioderegion; and implanting impurities into the diode region so as to form aP type photodiode at a surface of the diode region on the N typephotodiode.
 12. The method of claim 11, further comprising: beforeforming the photodiode, forming a deep P well in the substrate; formingP well in the substrate adjacent to the diode region; and before formingthe transfer gate, forming an N type channel diffusion layer in anactive region beneath the transfer gate, wherein the N type photodiodeis formed in the substrate on the deep P well to be connected to the Ntype channel diffusion layer and the P type photodiode is connected tothe P well adjacent to the diode region.
 13. The method of claim 9,wherein the forming the sidewall spacers and the blocking layercomprises: forming an insulation layer on an entire surface of thesubstrate with the lightly dope diffusion layers and the floatingdiffusion layer; forming a photoresist pattern covering tops of thediode region, the transfer gate and the floating diffusion layer;anisotropically etching the insulation layer using the photoresistpattern as an etch mask; and removing the photoresist pattern.
 14. Themethod of claim 9, wherein the lightly doped diffusion layer, thefloating diffusion layer and the heavily doped diffusion layer areformed by implanting impurities into the active region.
 15. The methodof claim 9, wherein after forming the heavily doped diffusion layers,further comprising: forming a mask insulation layer on the blockinglayer and mask spacers on the sidewall spacers; and applying asilicidation process to the substrate to form a salicide layer alignedto outer surfaces of the mask spacers in the heavily doped diffusionlayer.